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Udemy VSD Physical Design Flow

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Downloads: 5
Type: Tutorials
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Udemy VSD Physical Design Flow
Language: English
Category: Other
Size: 1.5 GB
Added: Oct. 23, 2023, 11:42 p.m.
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Files:
  1. Get Bonus Downloads Here.url 180 bytes
  2. 001 Floor-Planning Steps.mp4 11.9 MB
  3. 001 Floor-Planning Steps_en.vtt 14.9 KB
  4. 002 Netlist Binding And Placement Optimization.mp4 15.2 MB
  5. 002 Netlist Binding And Placement Optimization_en.vtt 13.1 KB
  6. 003 Placement Timing And Clock Tree Synthesis.mp4 18.3 MB
  7. 003 Placement Timing And Clock Tree Synthesis_en.vtt 12.7 KB
  8. 004 Clock Net Shielding.mp4 14.7 MB
  9. 004 Clock Net Shielding_en.vtt 13.6 KB
  10. 005 Route - DRC Clean - Parasitics Extraction - Final STA.mp4 22.2 MB
  11. 005 Route - DRC Clean - Parasitics Extraction - Final STA_en.vtt 12.7 KB
  12. 001 Utilization Factor And Aspect Ratio.mp4 8.9 MB
  13. 001 Utilization Factor And Aspect Ratio_en.vtt 12.5 KB
  14. 002 Concept Of Pre-Placed Cells.mp4 8.8 MB
  15. 002 Concept Of Pre-Placed Cells_en.vtt 13.3 KB
  16. 003 De-coupling Capacitors.mp4 11.4 MB
  17. 003 De-coupling Capacitors_en.vtt 13.5 KB
  18. 004 Power Planning.mp4 12.3 MB
  19. 004 Power Planning_en.vtt 15.0 KB
  20. 005 Pin Placement And Logical Cell Placement Blockage.mp4 46.2 MB
  21. 005 Pin Placement And Logical Cell Placement Blockage_en.vtt 13.6 KB
  22. 001 Net-list Binding And Placement.mp4 46.3 MB
  23. 001 Net-list Binding And Placement_en.vtt 13.2 KB
  24. 002 Optimize Placement Using Estimated Wire Length And Capacitance.mp4 91.3 MB
  25. 002 Optimize Placement Using Estimated Wire Length And Capacitance_en.vtt 14.4 KB
  26. 003 Optimize Placement Conitnued.mp4 86.9 MB
  27. 003 Optimize Placement Conitnued_en.vtt 12.1 KB
  28. 001 Setup Timing Analysis And Introduction to Flip-Flop Setup Time.mp4 31.5 MB
  29. 001 Setup Timing Analysis And Introduction to Flip-Flop Setup Time_en.vtt 13.2 KB
  30. 002 Introduction To Clock Jitter and Uncertainty.mp4 41.0 MB
  31. 002 Introduction To Clock Jitter and Uncertainty_en.vtt 10.6 KB
  32. 003 Setup Timing Analysis with Multiple Clocks.mp4 34.4 MB
  33. 003 Setup Timing Analysis with Multiple Clocks_en.vtt 11.7 KB
  34. 004 Multiple Clock Timing Analysis And Introduction To Data Slew Check.mp4 72.8 MB
  35. 004 Multiple Clock Timing Analysis And Introduction To Data Slew Check_en.vtt 12.5 KB
  36. 005 Data Slew Check.mp4 82.8 MB
  37. 005 Data Slew Check_en.vtt 13.0 KB
  38. 001 Clock Tree Routing And Buffering using H-Tree Algorithm.mp4 66.5 MB
  39. 001 Clock Tree Routing And Buffering using H-Tree Algorithm_en.vtt 12.9 KB
  40. 002 Crosstalk And Clock Net Shielding.mp4 59.2 MB
  41. 002 Crosstalk And Clock Net Shielding_en.vtt 13.0 KB
  42. 003 Static Timing Analysis With Real Clocks.mp4 47.7 MB
  43. 003 Static Timing Analysis With Real Clocks_en.vtt 15.9 KB
  44. 004 Hold Timing Analysis Concluded.mp4 74.5 MB
  45. 004 Hold Timing Analysis Concluded_en.vtt 14.1 KB
  46. 005 Multiple Clocks Setup Timing Analysis With Real Clocks.mp4 58.0 MB
  47. 005 Multiple Clocks Setup Timing Analysis With Real Clocks_en.vtt 11.4 KB
  48. 001 Introduction to Maze Routing - Lee's Algorithm.mp4 88.2 MB
  49. 001 Introduction to Maze Routing - Lee's Algorithm_en.vtt 12.4 KB
  50. 002 Lee's Algorithm Conclusion.mp4 114.9 MB
  51. 002 Lee's Algorithm Conclusion_en.vtt 14.0 KB
  52. 003 Design Rule Check.mp4 99.5 MB
  53. 003 Design Rule Check_en.vtt 13.7 KB
  54. 001 Introduction to IEEE 1481 - 1999 SPEF format.mp4 78.6 MB
  55. 001 Introduction to IEEE 1481 - 1999 SPEF format_en.vtt 12.5 KB
  56. 002 SPEF Representation of a NET.mp4 65.8 MB
  57. 002 SPEF Representation of a NET_en.vtt 11.3 KB
  58. 003 Distributed Resistance And Capacitance Representation in SPEF.mp4 79.0 MB
  59. 003 Distributed Resistance And Capacitance Representation in SPEF_en.vtt 14.2 KB
  60. 004 SPEF Header Description, Physical Design Flow Conclusion and What Next !!.mp4 41.7 MB
  61. 004 SPEF Header Description, Physical Design Flow Conclusion and What Next !!_en.vtt 11.9 KB
  62. Bonus Resources.txt 386 bytes

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