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Udemy Verilog HDL programming with practical approach

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Udemy Verilog HDL programming with practical approach
Language: English
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Added: Oct. 24, 2023, 4:05 a.m.
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Files:
  1. Get Bonus Downloads Here.url 182 bytes
  2. 001 Preview.mp4 84.6 MB
  3. 001 Preview_en.vtt 15.0 KB
  4. 002 Sample program on edaplayground.mp4 87.8 MB
  5. 002 Sample program on edaplayground_en.vtt 13.1 KB
  6. 001 Verilog fundamentals.mp4 165.6 MB
  7. 001 Verilog fundamentals_en.vtt 30.0 KB
  8. 001 VLSI Design flow (FPGA & ASIC).mp4 76.5 MB
  9. 001 VLSI Design flow (FPGA & ASIC)_en.vtt 14.3 KB
  10. 002 FPGA vs ASIC.mp4 80.1 MB
  11. 002 FPGA vs ASIC_en.vtt 8.7 KB
  12. 001 Three levels of verilog design Description.mp4 32.9 MB
  13. 001 Three levels of verilog design Description_en.vtt 3.7 KB
  14. 002 Example mux_2x1 with 3 abstracts models.mp4 9.1 MB
  15. 002 Example mux_2x1 with 3 abstracts models_en.vtt 1.8 KB
  16. 001 Language constructs -Comments, keywords, identifier, Number specific, Operators.mp4 14.5 MB
  17. 001 Language constructs -Comments, keywords, identifier, Number specific, Operators_en.vtt 2.2 KB
  18. 002 Datatypes - net,reg, integer, real, string, time, Parameter, Vector,Array,Memory.mp4 17.8 MB
  19. 002 Datatypes - net,reg, integer, real, string, time, Parameter, Vector,Array,Memory_en.vtt 3.0 KB
  20. 003 Compiler Directives.mp4 15.9 MB
  21. 003 Compiler Directives_en.vtt 2.0 KB
  22. 001 Verilog Program Structure -Module.mp4 7.4 MB
  23. 001 Verilog Program Structure -Module_en.vtt 1.1 KB
  24. 002 Ports.mp4 10.7 MB
  25. 002 Ports_en.vtt 1.8 KB
  26. 003 Port Connection Rules.mp4 13.0 MB
  27. 003 Port Connection Rules_en.vtt 1.9 KB
  28. 004 Design Methodologies Approaches.mp4 4.7 MB
  29. 004 Design Methodologies Approaches_en.vtt 849 bytes
  30. 001 Gate Level Model Introduction.mp4 3.4 MB
  31. 001 Gate Level Model Introduction_en.vtt 655 bytes
  32. 002 Example 4x1 Mux.mp4 5.4 MB
  33. 002 Example 4x1 Mux_en.vtt 932 bytes
  34. 003 Example Full Adder.mp4 3.6 MB
  35. 003 Example Full Adder_en.vtt 733 bytes
  36. 004 Tri-state Buffers with Examples.mp4 12.9 MB
  37. 004 Tri-state Buffers with Examples_en.vtt 2.0 KB
  38. 005 Array of Instance with example.mp4 10.7 MB
  39. 005 Array of Instance with example_en.vtt 1.6 KB
  40. 001 Data flow Modeling assign statement.mp4 12.9 MB
  41. 001 Data flow Modeling assign statement_en.vtt 2.3 KB
  42. 002 Operators.mp4 17.2 MB
  43. 002 Operators_en.vtt 1.9 KB
  44. 003 Arithmetic Operators.mp4 8.5 MB
  45. 003 Arithmetic Operators_en.vtt 1.4 KB
  46. 004 Logical Operators.mp4 12.7 MB
  47. 004 Logical Operators_en.vtt 1.6 KB
  48. 005 Example Full Adder Logical operators.mp4 3.8 MB
  49. 005 Example Full Adder Logical operators_en.vtt 811 bytes
  50. 006 Example Full Adder Arithmetic operators.mp4 2.8 MB
  51. 006 Example Full Adder Arithmetic operators_en.vtt 776 bytes
  52. 007 Example Binary to Gray code converter.mp4 4.6 MB
  53. 007 Example Binary to Gray code converter_en.vtt 891 bytes
  54. 008 Logical and , Logical or (&&, ).mp4 5.6 MB
  55. 008 Logical and , Logical or (&&, )_en.vtt 1.4 KB
  56. 009 Shift operators Leftright Shift.mp4 17.9 MB
  57. 009 Shift operators Leftright Shift_en.vtt 2.3 KB
  58. 010 Shifting without shift operator , just with concatenation operator.mp4 4.3 MB
  59. 010 Shifting without shift operator , just with concatenation operator_en.vtt 1.3 KB
  60. 011 Ternary operator Example 2x1 MUX, 4x1 MUX.mp4 13.6 MB
  61. 011 Ternary operator Example 2x1 MUX, 4x1 MUX_en.vtt 3.2 KB
  62. 012 Relational operators Example Comparator.mp4 4.5 MB
  63. 012 Relational operators Example Comparator_en.vtt 854 bytes
  64. 013 Equality (==) , case Equality (===) operators.mp4 7.1 MB
  65. 013 Equality (==) , case Equality (===) operators_en.vtt 1.9 KB
  66. 014 Reduction operator Example Parity Generator.mp4 7.1 MB
  67. 014 Reduction operator Example Parity Generator_en.vtt 1.3 KB
  68. 38061230-arthm1.mp4 3.8 MB
  69. 001 Behavioral Modeling - Introduction.mp4 67.0 MB
  70. 001 Behavioral Modeling - Introduction_en.vtt 7.8 KB
  71. 002 Behavioral Modeling Constructs.mp4 15.4 MB
  72. 002 Behavioral Modeling Constructs_en.vtt 1.8 KB
  73. 003 Procedural Blocks- initial & always.mp4 61.1 MB
  74. 003 Procedural Blocks- initial & always_en.vtt 7.6 KB
  75. 004 Example Clock Generation.mp4 8.4 MB
  76. 004 Example Clock Generation_en.vtt 2.1 KB
  77. 005 Assignment Statements - Blocking & Non-blocking.mp4 63.3 MB
  78. 005 Assignment Statements - Blocking & Non-blocking_en.vtt 7.0 KB
  79. 006 Mechanism in Non-blocking.mp4 4.4 MB
  80. 006 Mechanism in Non-blocking_en.vtt 1.2 KB
  81. 007 Concurrency.mp4 6.4 MB
  82. 007 Concurrency_en.vtt 1.2 KB
  83. 008 Advantage of Non-blocking assignment Example swapping.mp4 10.2 MB
  84. 008 Advantage of Non-blocking assignment Example swapping_en.vtt 1.4 KB
  85. 009 Advantage of Non-blocking assignment Example Pipelining.mp4 38.4 MB
  86. 009 Advantage of Non-blocking assignment Example Pipelining_en.vtt 5.6 KB
  87. 010 if-else statement Example 4x1 Mux.mp4 30.4 MB
  88. 010 if-else statement Example 4x1 Mux_en.vtt 4.3 KB
  89. 011 Case – statement Example 4x1 Mux.mp4 34.1 MB
  90. 011 Case – statement Example 4x1 Mux_en.vtt 3.6 KB
  91. 012 Advantage of Case over if-else.mp4 8.0 MB
  92. 012 Advantage of Case over if-else_en.vtt 1.0 KB
  93. 013 Loops while, for, repeat, forever.mp4 7.2 MB
  94. 013 Loops while, for, repeat, forever_en.vtt 1.4 KB
  95. 014 Parallel blocks - fork-join.mp4 10.8 MB
  96. 014 Parallel blocks - fork-join_en.vtt 1.7 KB
  97. 015 Combinational Logic Circuit Examples 8x1 Mux.mp4 7.6 MB
  98. 015 Combinational Logic Circuit Examples 8x1 Mux_en.vtt 1.8 KB
  99. 016 Example 8x1 Mux using 4x1 mux and 2x1 mux.mp4 16.9 MB
  100. 016 Example 8x1 Mux using 4x1 mux and 2x1 mux_en.vtt 2.6 KB
  101. 017 Example AND gate using 2x1 Mux.mp4 5.6 MB
  102. 017 Example AND gate using 2x1 Mux_en.vtt 2.1 KB
  103. 018 Example 1x8 Demux.mp4 3.4 MB
  104. 018 Example 1x8 Demux_en.vtt 704 bytes
  105. 019 Example Full Adder & 4-bit Full Adder.mp4 17.0 MB
  106. 019 Example Full Adder & 4-bit Full Adder_en.vtt 3.1 KB
  107. 020 Example 3x8 Decoder and 3x8 Decoder using 2x4 decoder.mp4 10.3 MB
  108. 020 Example 3x8 Decoder and 3x8 Decoder using 2x4 decoder_en.vtt 2.0 KB
  109. 021 Example 8x3 encoder.mp4 2.4 MB
  110. 021 Example 8x3 encoder_en.vtt 477 bytes
  111. 022 Example Priority encoder.mp4 7.8 MB
  112. 022 Example Priority encoder_en.vtt 1.4 KB
  113. 023 Example Seven Segment Display.mp4 13.4 MB
  114. 023 Example Seven Segment Display_en.vtt 1.9 KB
  115. 024 Example ALU.mp4 5.4 MB
  116. 024 Example ALU_en.vtt 863 bytes
  117. 025 Sequential Logic Circuits List of Examples.mp4 8.1 MB
  118. 025 Sequential Logic Circuits List of Examples_en.vtt 1.1 KB
  119. 026 Example D Flip Flop vs D-Latch.mp4 17.1 MB
  120. 026 Example D Flip Flop vs D-Latch_en.vtt 2.1 KB
  121. 027 Example Synchronous Reset D-Flip flop , Asynchronous Reset D-Flip flop.mp4 4.1 MB
  122. 027 Example Synchronous Reset D-Flip flop , Asynchronous Reset D-Flip flop_en.vtt 1.2 KB
  123. 028 Example T-Flip Flop.mp4 8.1 MB
  124. 028 Example T-Flip Flop_en.vtt 2.2 KB
  125. 029 Example Master-slave JK Flip Flop.mp4 6.1 MB
  126. 029 Example Master-slave JK Flip Flop_en.vtt 1.3 KB
  127. 030 Example Counter.mp4 19.4 MB
  128. 030 Example Counter_en.vtt 3.7 KB
  129. 031 Example UPDown Counter.mp4 27.4 MB
  130. 031 Example UPDown Counter_en.vtt 4.1 KB
  131. 032 Example clock divider using counter- Divide by 2,4,8,.mp4 13.6 MB
  132. 032 Example clock divider using counter- Divide by 2,4,8,_en.vtt 1.7 KB
  133. 033 Example Pulse Generator Mod-3 pulse generator.mp4 18.9 MB
  134. 033 Example Pulse Generator Mod-3 pulse generator_en.vtt 2.0 KB
  135. 034 Example Divide by 3 clock.mp4 17.7 MB
  136. 034 Example Divide by 3 clock_en.vtt 2.4 KB
  137. 035 Example Ring Counter vs Jonson Counter.mp4 11.8 MB
  138. 035 Example Ring Counter vs Jonson Counter_en.vtt 1.9 KB
  139. 036 Example Shift Registers SISO, SIPO, PISO,PIPO.mp4 13.3 MB
  140. 036 Example Shift Registers SISO, SIPO, PISO,PIPO_en.vtt 1.7 KB
  141. 037 Example LFSR (Linear Feedback Shift Register).mp4 35.1 MB
  142. 037 Example LFSR (Linear Feedback Shift Register)_en.vtt 5.1 KB
  143. 038 memory design.mp4 27.0 MB
  144. 038 memory design_en.vtt 3.8 KB
  145. 001 Switch level modeling.mp4 17.7 MB
  146. 001 Switch level modeling_en.vtt 3.2 KB
  147. 001 Functional simulation.mp4 27.0 MB
  148. 001 Functional simulation_en.vtt 4.6 KB
  149. 002 Example - Test bench for counter design.mp4 62.4 MB
  150. 002 Example - Test bench for counter design_en.vtt 5.4 KB
  151. 003 Example - Test bench for Pulse generator.mp4 58.3 MB
  152. 003 Example - Test bench for Pulse generator_en.vtt 5.6 KB
  153. external-assets-links.txt 412 bytes
  154. 001 Functions & tasks and system tasks.mp4 49.7 MB
  155. 001 Functions & tasks and system tasks_en.vtt 5.6 KB
  156. 002 File based system tasks and random generator system task.mp4 68.5 MB
  157. 002 File based system tasks and random generator system task_en.vtt 7.4 KB
  158. 003 Read file and write in to memory system task.mp4 18.9 MB
  159. 003 Read file and write in to memory system task_en.vtt 2.0 KB
  160. 004 Programming Language Interface.mp4 13.5 MB
  161. 004 Programming Language Interface_en.vtt 1.3 KB
  162. external-assets-links.txt 633 bytes
  163. 001 FSM ( Finite State Machine) & Hardware modeling of FSM, Example Verilog code.mp4 126.4 MB
  164. 001 FSM ( Finite State Machine) & Hardware modeling of FSM, Example Verilog code_en.vtt 22.6 KB
  165. 002 Example FSM - Divide by 2 clock.mp4 11.5 MB
  166. 002 Example FSM - Divide by 2 clock_en.vtt 1.9 KB
  167. 003 Example FSM- Divide by 3 clock.mp4 22.5 MB
  168. 003 Example FSM- Divide by 3 clock_en.vtt 2.6 KB
  169. 001 Sequence detector using FSM with complete Design & TB.mp4 65.0 MB
  170. 001 Sequence detector using FSM with complete Design & TB_en.vtt 8.9 KB
  171. 002 Sequence detector using FSM output waveform.mp4 13.3 MB
  172. 002 Sequence detector using FSM output waveform_en.vtt 1.2 KB
  173. external-assets-links.txt 212 bytes
  174. 001 Memory controller with Design & TB.mp4 92.8 MB
  175. 001 Memory controller with Design & TB_en.vtt 10.0 KB
  176. external-assets-links.txt 212 bytes
  177. 001 FIFO Lecture.mp4 1.1 MB
  178. 001 FIFO Lecture_en.vtt 60 bytes
  179. 002 Introduction to FIFO.mp4 32.4 MB
  180. 002 Introduction to FIFO_en.vtt 4.4 KB
  181. 003 Write Read Operation of Normal RAM.mp4 27.0 MB
  182. 003 Write Read Operation of Normal RAM_en.vtt 3.8 KB
  183. 004 FIFO IO (input & Outputs).mp4 8.0 MB
  184. 004 FIFO IO (input & Outputs)_en.vtt 1.4 KB
  185. 005 Block Diagram and Architecture of FIFO.mp4 44.5 MB
  186. 005 Block Diagram and Architecture of FIFO_en.vtt 4.2 KB
  187. 006 Connection of FIFO design & Test bench environment.mp4 18.6 MB
  188. 006 Connection of FIFO design & Test bench environment_en.vtt 3.1 KB
  189. 007 Verilog HDL for FIFO design.mp4 89.4 MB
  190. 007 Verilog HDL for FIFO design_en.vtt 12.4 KB
  191. 008 Verilog HDL code for FIFO Test Bench.mp4 147.8 MB
  192. 008 Verilog HDL code for FIFO Test Bench_en.vtt 15.3 KB
  193. 009 Run the simulation and finding errors and Analyze the waveform Results.mp4 61.2 MB
  194. 009 Run the simulation and finding errors and Analyze the waveform Results_en.vtt 6.8 KB
  195. external-assets-links.txt 78 bytes
  196. 001 Hamming code complete Design & TB for error detection & correction.mp4 213.7 MB
  197. 001 Hamming code complete Design & TB for error detection & correction_en.vtt 19.5 KB
  198. external-assets-links.txt 689 bytes
  199. 001 FPGA.mp4 131.7 MB
  200. 001 FPGA_en.vtt 14.9 KB
  201. Bonus Resources.txt 386 bytes

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